VAESENCLAST

REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128

x86_64 X86_LEGACY AES VAES source: xed

XED_VAESENCLAST_YMMu128_YMMu128_YMMu128

Encoding

encoding_kindX86_LEGACY
opcode_bytesDD
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l1
exception_classavx-type-4
cpl3
raw_encodingVV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256

Operands (3)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG R EXPLICIT MODRM_REG
2 REG2 REG R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.