VBLENDVPS

REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:u32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:u32 REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:u32 REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:u32

x86_64 X86_LEGACY AVX AVX source: xed

XED_VBLENDVPS_X86_LEGACY_ONEBYTE_4A_28339

Encoding

encoding_kindX86_LEGACY
opcode_bytes4A 4A 4A 4A
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l1
exception_classavx-type-4
cpl3
raw_encodingVV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()

Operands (16)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG f32 R EXPLICIT MODRM_REG
2 MEM0 MEM f32 R EXPLICIT MODRM_RM
3 REG2 REG R EXPLICIT MODRM_REG
4 REG3 REG w W EXPLICIT MODRM_REG
5 REG4 REG f32 R EXPLICIT MODRM_REG
6 REG5 REG f32 R EXPLICIT MODRM_REG
7 REG6 REG R EXPLICIT MODRM_REG
8 REG7 REG w W EXPLICIT MODRM_REG
9 REG8 REG f32 R EXPLICIT MODRM_REG
10 MEM1 MEM f32 R EXPLICIT MODRM_RM
11 REG9 REG R EXPLICIT MODRM_REG
12 REG10 REG w W EXPLICIT MODRM_REG
13 REG11 REG f32 R EXPLICIT MODRM_REG
14 REG12 REG f32 R EXPLICIT MODRM_REG
15 REG13 REG R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.