VBROADCASTI32X2
BROADCAST AVX512DQ_128 x86_64
VBROADCASTI32X2 is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category BROADCAST. This page lists its 6 encoding forms, distinguished by opcode byte: 59.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32
XED_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32
XED_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32
XED_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32
XED_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32
XED_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32