VCMPBF16
AVX512 AVX10_2_BF16_128 x86_64
6 encoding forms.
XED_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
XED_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16 IMM0:r:b
XED_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
XED_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16 IMM0:r:b
XED_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
XED_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16 IMM0:r:b