VCMPPH
FP16 AVX512_FP16_128 x86_64
6 encoding forms.
XED_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
XED_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
XED_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
XED_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b
XED_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
XED_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b