VCMPPS
AVX512 AVX512F_128 x86_64
VCMPPS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 7 encoding forms, distinguished by opcode byte: C2.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
XED_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
XED_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
XED_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
XED_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
XED_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
XED_VCMPPS_X86_LEGACY_ONEBYTE_C2_676506
REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b