VCOMPRESSPD
COMPRESS AVX512F_128 x86_64
VCOMPRESSPD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category COMPRESS. This page lists its 6 encoding forms, distinguished by opcode byte: 8A.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512
MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
XED_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512
MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
XED_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512
MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
XED_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512
REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64
XED_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512
REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64
XED_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512
REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64