VCVT2PH2BF8S
CONVERT AVX512_FP8_CONVERT_128 x86_64
6 encoding forms.
XED_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512
REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512
REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
XED_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512
REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512
REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
XED_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512
REG0=ZMM_R3():w:zbf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512
REG0=ZMM_R3():w:zbf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16