VCVTBIASPH2HF8
CONVERT AVX512_FP8_CONVERT_128 x86_64
6 encoding forms.
XED_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 REG3=XMM_B3():r:dq:f16
XED_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 REG3=YMM_B3():r:qq:f16
XED_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512
REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512
REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 REG3=ZMM_B3():r:zf16