VCVTBIASPH2HF8S
CONVERT AVX512_FP8_CONVERT_128 x86_64
VCVTBIASPH2HF8S is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 6 encoding forms, distinguished by opcode byte: 1B.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2i8 REG3=XMM_B3():r:dq:f16
XED_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512
REG0=XMM_R3():w:dq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2i8 REG3=YMM_B3():r:qq:f16
XED_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512
REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512
REG0=YMM_R3():w:qq:hf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2i8 REG3=ZMM_B3():r:zf16