VCVTNEPS2BF16
CONVERT AVX_NE_CONVERT x86_64
VCVTNEPS2BF16 is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 10 encoding forms, distinguished by opcode byte: 72.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
XED_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
XED_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
XED_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
XED_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128
REG0=XMM_R():w:dq:bf16 MEM0:r:dq:f32
XED_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256
REG0=XMM_R():w:dq:bf16 MEM0:r:qq:f32
XED_VCVTNEPS2BF16_XMMbf16_XMMf32
REG0=XMM_R():w:dq:bf16 REG1=XMM_B():r:dq:f32
XED_VCVTNEPS2BF16_XMMbf16_YMMf32
REG0=XMM_R():w:dq:bf16 REG1=YMM_B():r:qq:f32
XED_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512
REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
XED_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512
REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32