VCVTPD2DQ

CONVERT AVX512F_128 x86_64

7 encoding forms.

XED_VCVTPD2DQ_X86_LEGACY_ONEBYTE_E6_956358
REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64
X86_LEGACY E6 E6 E6 E6 /r AVX
XED_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
X86_LEGACY E6 /r AVX512F_128
XED_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
X86_LEGACY E6 /r AVX512F_256
XED_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
X86_LEGACY E6 /r AVX512F_128
XED_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
X86_LEGACY E6 /r AVX512F_256
XED_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
X86_LEGACY E6 /r AVX512F_512
XED_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
X86_LEGACY E6 /r AVX512F_512