VCVTPD2UDQ
CONVERT AVX512F_128 x86_64
6 encoding forms.
XED_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
XED_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
XED_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
XED_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
XED_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
XED_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64