VCVTPH2BF8

CONVERT AVX512_FP8_CONVERT_128 x86_64

6 encoding forms.

XED_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128
REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
X86_LEGACY 74 /r AVX512_FP8_CONVERT_128
XED_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256
REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
X86_LEGACY 74 /r AVX512_FP8_CONVERT_256
XED_VCVTPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512
REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
X86_LEGACY 74 /r AVX512_FP8_CONVERT_128
XED_VCVTPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512
REG0=XMM_R3():w:dq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
X86_LEGACY 74 /r AVX512_FP8_CONVERT_256
XED_VCVTPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512
REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
X86_LEGACY 74 /r AVX512_FP8_CONVERT_512
XED_VCVTPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512
REG0=YMM_R3():w:qq:bf8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
X86_LEGACY 74 /r AVX512_FP8_CONVERT_512