VCVTQQ2PD
CONVERT AVX512DQ_128 x86_64
VCVTQQ2PD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 6 encoding forms, distinguished by opcode byte: E6.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
XED_VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64
XED_VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
XED_VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64
XED_VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
XED_VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64