VCVTQQ2PD

CONVERT AVX512DQ_128 x86_64

6 encoding forms.

XED_VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
X86_LEGACY E6 /r AVX512DQ_128
XED_VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64
X86_LEGACY E6 /r AVX512DQ_128
XED_VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
X86_LEGACY E6 /r AVX512DQ_256
XED_VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64
X86_LEGACY E6 /r AVX512DQ_256
XED_VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
X86_LEGACY E6 /r AVX512DQ_512
XED_VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64
X86_LEGACY E6 /r AVX512DQ_512