VCVTTBF162IBS
CONVERT AVX512_SAT_CVT_128 x86_64
VCVTTBF162IBS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 6 encoding forms, distinguished by opcode byte: 68.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512
REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VCVTTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512
REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
XED_VCVTTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512
REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VCVTTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512
REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
XED_VCVTTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512
REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VCVTTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512
REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16