VCVTTPD2UQQ

CONVERT AVX512DQ_128 x86_64

6 encoding forms.

XED_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
X86_LEGACY 78 /r AVX512DQ_128
XED_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
X86_LEGACY 78 /r AVX512DQ_128
XED_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
X86_LEGACY 78 /r AVX512DQ_256
XED_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
X86_LEGACY 78 /r AVX512DQ_256
XED_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
X86_LEGACY 78 /r AVX512DQ_512
XED_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
X86_LEGACY 78 /r AVX512DQ_512