VCVTTPH2UQQ

CONVERT AVX512_FP16_128 x86_64

6 encoding forms.

XED_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
X86_LEGACY 78 /r AVX512_FP16_128
XED_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
X86_LEGACY 78 /r AVX512_FP16_128
XED_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
X86_LEGACY 78 /r AVX512_FP16_256
XED_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
X86_LEGACY 78 /r AVX512_FP16_256
XED_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
X86_LEGACY 78 /r AVX512_FP16_512
XED_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
X86_LEGACY 78 /r AVX512_FP16_512