VCVTTPH2UW
CONVERT AVX512_FP16_128 x86_64
VCVTTPH2UW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 6 encoding forms, distinguished by opcode byte: 7C.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
XED_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
XED_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
XED_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16