VCVTTPS2UDQS

CONVERT AVX512_SAT_CVT_DS_128 x86_64

6 encoding forms.

XED_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
X86_LEGACY 6C /r AVX512_SAT_CVT_DS_128
XED_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
X86_LEGACY 6C /r AVX512_SAT_CVT_DS_128
XED_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
X86_LEGACY 6C /r AVX512_SAT_CVT_DS_256
XED_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
X86_LEGACY 6C /r AVX512_SAT_CVT_DS_256
XED_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
X86_LEGACY 6C /r AVX512_SAT_CVT_DS_512
XED_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
X86_LEGACY 6C /r AVX512_SAT_CVT_DS_512