VCVTTPS2UQQS
CONVERT AVX512_SAT_CVT_DS_128 x86_64
VCVTTPS2UQQS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 6 encoding forms, distinguished by opcode byte: 6C.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
XED_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
XED_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
XED_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
XED_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
XED_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32