VCVTTSS2SI
REG0=VGPR32_R():w:d:i32 MEM0:r:d:f32 REG0=VGPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 REG0=VGPR32_R():w:d:i32 MEM0:r:d:f32 REG0=VGPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 REG0=VGPR64_R():w:q:i64 MEM0:r:d:f32 REG0=VGPR64_R():w:q:i64 REG1=XMM_B():r:d:f32
x86_64 X86_LEGACY CONVERT AVX source: xed
XED_VCVTTSS2SI_X86_LEGACY_ONEBYTE_2C_587761
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 2C 2C 2C 2C 2C 2C |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| rex_w | 1 |
| requires_mode | long |
| attributes | simd_scalar MXCSR |
| exception_class | avx-type-3 |
| cpl | 3 |
| raw_encoding | VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] |
Operands (12)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | MEM0 | MEM | d | R | EXPLICIT | MODRM_RM | |
| 2 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 3 | REG2 | REG | d | R | EXPLICIT | MODRM_REG | |
| 4 | REG3 | REG | w | W | EXPLICIT | MODRM_REG | |
| 5 | MEM1 | MEM | d | R | EXPLICIT | MODRM_RM | |
| 6 | REG4 | REG | w | W | EXPLICIT | MODRM_REG | |
| 7 | REG5 | REG | d | R | EXPLICIT | MODRM_REG | |
| 8 | REG6 | REG | w | W | EXPLICIT | MODRM_REG | |
| 9 | MEM2 | MEM | d | R | EXPLICIT | MODRM_RM | |
| 10 | REG7 | REG | w | W | EXPLICIT | MODRM_REG | |
| 11 | REG8 | REG | d | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.