VCVTTSS2SIS
CONVERT AVX512_SAT_CVT_DS_SCALAR x86_64
VCVTTSS2SIS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 4 encoding forms, distinguished by opcode byte: 6D.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512
REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
XED_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512
REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
XED_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512
REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
XED_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512
REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32