VCVTUDQ2PD
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
x86_64 X86_LEGACY CONVERT AVX512F_512 source: xed
XED_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 7A 7A |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 2 |
| attributes | MASKOP_EVEX |
| exception_class | AVX512-E5 |
| cpl | 3 |
| raw_encoding | EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] VL512 W0 NOEVSR EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 3 | REG3 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | REG4 | REG | R | EXPLICIT | MODRM_REG | ||
| 5 | REG5 | REG | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.