VCVTUDQ2PS

CONVERT AVX512F_128 x86_64

6 encoding forms.

XED_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
X86_LEGACY 7A /r AVX512F_128
XED_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
X86_LEGACY 7A /r AVX512F_128
XED_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
X86_LEGACY 7A /r AVX512F_256
XED_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
X86_LEGACY 7A /r AVX512F_256
XED_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
X86_LEGACY 7A /r AVX512F_512
XED_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
X86_LEGACY 7A /r AVX512F_512