VCVTUQQ2PH
CONVERT AVX512_FP16_128 x86_64
VCVTUQQ2PH is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 6 encoding forms, distinguished by opcode byte: 7A.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
XED_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
XED_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
XED_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
XED_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
XED_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64