VCVTUW2PH

CONVERT AVX512_FP16_128 x86_64

6 encoding forms.

XED_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
X86_LEGACY 7D /r AVX512_FP16_128
XED_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
X86_LEGACY 7D /r AVX512_FP16_128
XED_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512
REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
X86_LEGACY 7D /r AVX512_FP16_256
XED_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512
REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
X86_LEGACY 7D /r AVX512_FP16_256
XED_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512
REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
X86_LEGACY 7D /r AVX512_FP16_512
XED_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512
REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
X86_LEGACY 7D /r AVX512_FP16_512