VDPBF16PS
AVX512 AVX512_BF16_128 x86_64
VDPBF16PS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 6 encoding forms, distinguished by opcode byte: 52.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512
REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512
REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
XED_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512
REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512
REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
XED_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512
REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512
REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32