VDPPS
REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b
x86_64 X86_LEGACY AVX AVX source: xed
XED_VDPPS_X86_LEGACY_ONEBYTE_40_645634
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 40 40 40 40 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 1 |
| imm_size_bytes | 1 |
| attributes | MXCSR |
| exception_class | avx-type-2D |
| cpl | 3 |
| raw_encoding | VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() |
Operands (16)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 2 | MEM0 | MEM | f32 | R | EXPLICIT | MODRM_RM | |
| 3 | IMM0 | IMM | b | R | EXPLICIT | IMM | |
| 4 | REG2 | REG | w | W | EXPLICIT | MODRM_REG | |
| 5 | REG3 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 6 | REG4 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 7 | IMM1 | IMM | b | R | EXPLICIT | IMM | |
| 8 | REG5 | REG | w | W | EXPLICIT | MODRM_REG | |
| 9 | REG6 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 10 | MEM1 | MEM | f32 | R | EXPLICIT | MODRM_RM | |
| 11 | IMM2 | IMM | b | R | EXPLICIT | IMM | |
| 12 | REG7 | REG | w | W | EXPLICIT | MODRM_REG | |
| 13 | REG8 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 14 | REG9 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 15 | IMM3 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.