VEXPANDPD

EXPAND AVX512F_128 x86_64

6 encoding forms.

XED_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
X86_LEGACY 88 /r AVX512F_128
XED_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
X86_LEGACY 88 /r AVX512F_128
XED_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
X86_LEGACY 88 /r AVX512F_256
XED_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
X86_LEGACY 88 /r AVX512F_256
XED_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
X86_LEGACY 88 /r AVX512F_512
XED_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
X86_LEGACY 88 /r AVX512F_512