VEXTRACTF32X8
MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
x86_64 X86_LEGACY AVX512 AVX512DQ_512 source: xed
XED_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 1B |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 2 |
| imm_size_bytes | 1 |
| attributes | DISP8_TUPLE8 MASKOP_EVEX |
| exception_class | AVX512-E6NF |
| cpl | 3 |
| raw_encoding | EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 VL512 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | w | W | EXPLICIT | MODRM_RM | |
| 1 | REG0 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 3 | IMM0 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.