VFMADD213BF16
VFMA AVX10_2_BF16_128 x86_64
6 encoding forms.
XED_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512
REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512
REG0=XMM_R3():rw:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:bf16 REG3=XMM_B3():r:dq:bf16
XED_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512
REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512
REG0=YMM_R3():rw:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:bf16 REG3=YMM_B3():r:qq:bf16
XED_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512
REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512
REG0=ZMM_R3():rw:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zbf16 REG3=ZMM_B3():r:zbf16