VFMADDCPH
FP16 AVX512_FP16_128 x86_64
VFMADDCPH is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category FP16. This page lists its 6 encoding forms, distinguished by opcode byte: 56.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
XED_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
XED_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
XED_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
XED_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
XED_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16