VFMSUB231SS
VFMA AVX512F_SCALAR x86_64
VFMSUB231SS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category VFMA. This page lists its 3 encoding forms, distinguished by opcode byte: BB.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VFMSUB231SS_X86_LEGACY_ONEBYTE_BB_523110
REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
XED_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
XED_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32