VFMSUBADD231PD
VFMA AVX512F_128 x86_64
VFMSUBADD231PD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category VFMA. This page lists its 7 encoding forms, distinguished by opcode byte: B7.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VFMSUBADD231PD_X86_LEGACY_ONEBYTE_B7_407485
REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
XED_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
XED_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
XED_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
XED_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
XED_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
XED_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64