VFMULCSH
FP16 AVX512_FP16_SCALAR x86_64
VFMULCSH is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category FP16. This page lists its 2 encoding forms, distinguished by opcode byte: D7.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
XED_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16