VFPCLASSBF16

AVX512 AVX10_2_BF16_128 x86_64

6 encoding forms.

XED_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128
REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
X86_LEGACY 00 /r AVX10_2_BF16_128
XED_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256
REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
X86_LEGACY 00 /r AVX10_2_BF16_256
XED_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512
REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
X86_LEGACY 00 /r AVX10_2_BF16_512
XED_VFPCLASSBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:bf16 IMM0:r:b
X86_LEGACY 00 /r AVX10_2_BF16_128
XED_VFPCLASSBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:bf16 IMM0:r:b
X86_LEGACY 00 /r AVX10_2_BF16_256
XED_VFPCLASSBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512
REG0=MASK_R():w:mskw:i1 REG1=MASK1():r:mskw REG2=ZMM_B3():r:zbf16 IMM0:r:b
X86_LEGACY 00 /r AVX10_2_BF16_512