VFPCLASSPD
AVX512 AVX512DQ_128 x86_64
VFPCLASSPD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 6 encoding forms, distinguished by opcode byte: 00.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
XED_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
XED_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
XED_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
XED_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b
XED_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b