VFPCLASSSD
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
x86_64 X86_LEGACY AVX512 AVX512DQ_SCALAR source: xed
XED_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 67 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| imm_size_bytes | 1 |
| attributes | MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ |
| exception_class | AVX512-E10 |
| cpl | 3 |
| raw_encoding | EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() NOEVSR ZEROING=0 UIMM8() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | f64 | R | EXPLICIT | MODRM_REG | |
| 3 | IMM0 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.