VGATHERDPS

REG0=YMM_R():crw:qq:f32 MEM0:r:d:f32 REG1=YMM_N():rw:qq:i32 REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32

x86_64 X86_LEGACY GATHER AVX2GATHER source: xed

XED_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128

Encoding

encoding_kindX86_LEGACY
opcode_bytes92 92
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l0
attributesgather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED
exception_classavx-type-12
cpl3
raw_encodingVV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16

Operands (6)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG f32 R EXPLICIT MODRM_REG
1 MEM0 MEM d R EXPLICIT MODRM_RM
2 REG1 REG RW EXPLICIT MODRM_REG
3 REG2 REG f32 R EXPLICIT MODRM_REG
4 MEM1 MEM d R EXPLICIT MODRM_RM
5 REG3 REG RW EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.