VGETEXPBF16
AVX512 AVX10_2_BF16_128 x86_64
VGETEXPBF16 is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 6 encoding forms, distinguished by opcode byte: 42.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VGETEXPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VGETEXPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16
XED_VGETEXPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512
REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VGETEXPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512
REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16
XED_VGETEXPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512
REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR
XED_VGETEXPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512
REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16