VGF2P8MULB
GFNI AVX512_GFNI_128 x86_64
VGF2P8MULB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category GFNI. This page lists its 10 encoding forms, distinguished by opcode byte: CF.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
XED_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
XED_VGF2P8MULB_XMMu8_XMMu8_MEMu8
REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
XED_VGF2P8MULB_XMMu8_XMMu8_XMMu8
REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
XED_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
XED_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
XED_VGF2P8MULB_YMMu8_YMMu8_MEMu8
REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
XED_VGF2P8MULB_YMMu8_YMMu8_YMMu8
REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
XED_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
XED_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8