VINSERTI64X2
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
x86_64 X86_LEGACY AVX512 AVX512DQ_512 source: xed
XED_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 38 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 2 |
| imm_size_bytes | 1 |
| attributes | MASKOP_EVEX |
| exception_class | AVX512-E6NF |
| cpl | 3 |
| raw_encoding | EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL512 UIMM8() |
Operands (5)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 3 | REG3 | REG | R | EXPLICIT | MODRM_REG | ||
| 4 | IMM0 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.