VMINMAXPH
AVX512 AVX512_MINMAX_128 x86_64
VMINMAXPH is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 6 encoding forms, distinguished by opcode byte: 52.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
XED_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
XED_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512
REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
XED_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512
REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b
XED_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512
REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
XED_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b