VMINMAXPS

AVX512 AVX512_MINMAX_128 x86_64

6 encoding forms.

XED_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
X86_LEGACY 52 /r AVX512_MINMAX_128
XED_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
X86_LEGACY 52 /r AVX512_MINMAX_128
XED_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
X86_LEGACY 52 /r AVX512_MINMAX_256
XED_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
X86_LEGACY 52 /r AVX512_MINMAX_256
XED_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
X86_LEGACY 52 /r AVX512_MINMAX_512
XED_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
X86_LEGACY 52 /r AVX512_MINMAX_512