VMINSD
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
x86_64 X86_LEGACY AVX512 AVX512F_SCALAR source: xed
XED_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 5D |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| attributes | MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR |
| exception_class | AVX512-E3 |
| cpl | 3 |
| raw_encoding | EVV 0x5D VF2 V0F MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_ONE() FIX_ROUND_LEN128() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | f64 | R | EXPLICIT | MODRM_REG | |
| 3 | MEM0 | MEM | q | R | EXPLICIT | MODRM_RM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.