VMOVAPS
DATAXFER AVX512F_128 x86_64
VMOVAPS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 10 encoding forms, distinguished by opcode bytes: 28, 29.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512
MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
XED_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512
MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
XED_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512
MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
XED_VMOVAPS_XMMdq_XMMdq_28 VMOVAPS_XMMdq_XMMdq_29 VMOVAPS_YMMqq_YMMqq_28 VMOVAPS_YMMqq_YMMqq_29
REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32
XED_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
XED_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
XED_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
XED_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
XED_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
XED_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32