VMOVDQA32
DATAXFER AVX512F_128 x86_64
VMOVDQA32 is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 9 encoding forms, distinguished by opcode bytes: 6F, 7F.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512
MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
XED_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512
MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
XED_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512
MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
XED_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
XED_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
XED_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
XED_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
XED_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
XED_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32