VMOVDQU

REG0=XMM_R():w:dq MEM0:r:dq REG0=XMM_R():w:dq REG1=XMM_B():r:dq REG0=YMM_R():w:qq MEM0:r:qq REG0=YMM_R():w:qq REG1=YMM_B():r:qq MEM0:w:dq REG0=XMM_R():r:dq REG0=XMM_B():w:dq REG1=XMM_R():r:dq MEM0:w:qq REG0=YMM_R():r:qq REG0=YMM_B():w:qq REG1=YMM_R():r:qq

x86_64 X86_LEGACY DATAXFER AVX source: xed

XED_VMOVDQU_XMMdq_XMMdq_6F VMOVDQU_YMMqq_YMMqq_6F VMOVDQU_XMMdq_XMMdq_7F VMOVDQU_YMMqq_YMMqq_7F

Encoding

encoding_kindX86_LEGACY
opcode_bytes6F 6F 6F 6F 7F 7F 7F 7F
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l1
exception_classavx-type-4M
cpl3
raw_encodingVV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]

Operands (16)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 MEM0 MEM R EXPLICIT MODRM_RM
2 REG1 REG w W EXPLICIT MODRM_REG
3 REG2 REG R EXPLICIT MODRM_REG
4 REG3 REG w W EXPLICIT MODRM_REG
5 MEM1 MEM R EXPLICIT MODRM_RM
6 REG4 REG w W EXPLICIT MODRM_REG
7 REG5 REG R EXPLICIT MODRM_REG
8 MEM2 MEM w W EXPLICIT MODRM_RM
9 REG6 REG R EXPLICIT MODRM_REG
10 REG7 REG w W EXPLICIT MODRM_REG
11 REG8 REG R EXPLICIT MODRM_REG
12 MEM3 MEM w W EXPLICIT MODRM_RM
13 REG9 REG R EXPLICIT MODRM_REG
14 REG10 REG w W EXPLICIT MODRM_REG
15 REG11 REG R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.