VMOVDQU16
DATAXFER AVX512BW_128 x86_64
VMOVDQU16 is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 9 encoding forms, distinguished by opcode bytes: 6F, 7F.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512
MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
XED_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512
MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
XED_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512
MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
XED_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
XED_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
XED_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
XED_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
XED_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
XED_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16